1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly, to a semiconductor device including a silicon on insulator (SOI) device.
2. Description of the Related Art
An SOI device has a silicon substrate layer and a thin film silicon layer (hereinafter, referred to as an SOI layer) provided on the silicon substrate layer. The silicon substrate layer is separated from the thin film silicon layer by a buried oxide film layer (hereinafter, referred to as a BOX layer) in an insulated state. Consequently, it is possible to easily achieve insulative separation between neighboring elements. In addition, no parasitic thyristor is formed via the silicon substrate layer, with the result that it is possible to prevent the occurrence of a latch up phenomenon. When a transistor is mounted in the SOI layer on the BOX layer, it is possible to effectively restrain the occurrence of a so-called short channel effect. The short channel effect is a phenomenon in which power consumption increases with the downsizing of the transistor. Since the junction capacity of a transistor having an SOI structure is less than that of a transistor having a bulk structure, high-speed operation is possible in the SOI device. The transistor having the SOI structure is expected to exhibit many excellent properties and achieve higher speed and lower power consumption than a semiconductor element formed on a conventional bulk substrate. Attempts are being conducted to apply a wafer having the SOI structure (hereinafter, referred to as an SOI substrate) to an optical sensor, such as an ultraviolet (UV) sensor and an image sensor.
An optical sensor, such as a UV sensor and an image sensor, is mounted in a mobile device, such as a mobile phone. For this reason, the further reduction of a package size is needed. Therefore, a wafer level chip size package (W-CSP) having a through via is used as a package of such optical sensor. Since it is possible to form an external terminal at a back face (lower face), i.e., the surface opposite a light receiving surface, of the W-CSP having the through via, the external terminal can be arranged at a desired position without being affected by the light receiving area. This satisfies the demand for reduction of the package size.
When the W-CSP having the through via is applied to the SOI device, however, the following problems are caused. If the W-CSP is applied to the SOI device, the silicon substrate layer below the BOX layer is not connected to any external terminal, and the potential of the silicon substrate layer floats. When the potential of the silicon substrate layer is in a floating state, the operation of a circuit formed at the SOI layer may become unstable, with the result that the circuit may malfunction. Therefore, it is necessary to fix the potential of the silicon substrate layer by a suitable method.
An example of the method of fixing the potential of the silicon substrate layer of the SOI substrate is disclosed in Japanese Patent Application Kokai (Laid-Open) No. 7-335811. This fixing method relies upon a chip that is loaded on a lead frame fixed at ground potential via a conductive adhesive.
Japanese Patent Application Kokai No. 11-354631 discloses a semiconductor device having a conductive layer. The conductive layer extends through the SOI layer and the BOX layer from the upper surface of the SOI layer, and connects to the silicon substrate layer. A substrate potential fixing electrode is formed at the surface of the SOI layer. The substrate potential fixing electrode is electrically connected to the conductive layer.